參數(shù)資料
型號： MCF547X
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： MCF547x Integrated Microprocessor Electrical Characteristics
中文描述： MCF547x集成的微處理器，電氣特性
文件頁數(shù)： 15/28頁
文件大?。?/td> 706K
代理商： MCF547X
SDRAM Bus
MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
Freescale Semiconductor
15
Figure 10. DDR Clock Timing Diagram
Table 13. DDR Timing Specifications
Symbol
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
83
133
MHz
1
NOTES:
1
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see Section 2.2.6, “Reset Configuration Pins.”
2
SDCLK is one memory clock in (ns).
3
Pulse width high plus pulse width low cannot exceed max clock period.
4
Pulse width high plus pulse width low cannot exceed max clock period.
5
Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.
6
This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to
SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative
SDDQS0.
7
The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining
data beats will be valid for each subsequent SDDQS edge.
DD1
Clock Period (t
CK
)
Pulse Width High (t
CKH
)
Pulse Width Low (t
CKL
)
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output
Valid (t
CMV
)
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Hold
(t
CMH
)
Write Command to first DQS Latching Transition (t
DQSS
)
Data and Data Mask Output Setup (DQ
>
DQS) Relative to
DQS (DDR Write Mode) (t
QS
)
Data and Data Mask Output Hold (DQS
>
DQ) Relative to DQS
(DDR Write Mode) (t
QH
)
Input Data Skew Relative to DQS (Input Setup) (t
IS
)
Input Data Hold Relative to DQS (t
IH
)
7.52
12
ns
2
DD2
0.45
0.55
SDCLK
3
DD3
0.45
0.55
SDCLK
4
DD4
—
0.5
×
SDCLK
+ 1.0 ns
ns
5
DD5
2.0
—
ns
DD6
—
1.25
SDCLK
DD7
1.0
—
ns
6
7
DD8
1.0
—
ns
8
DD9
1
ns
9
DD10
0.25
×
SDCLK
+ 0.5ns
—
ns
10
DD11
DQS falling edge to SDCLK rising (output setup time) (t
DSS
)
DQS falling edge from SDCLK rising (output hold time) (t
DSH
)
DQS input read preamble width (t
RPRE
)
DQS input read postamble width (t
RPST
)
DQS output write preamble width (t
WPRE
)
DQS output write postamble width (t
WPST
)
0.5
—
ns
DD12
0.5
—
ns
DD13
0.9
1.1
SDCLK
DD14
0.4
0.6
SDCLK
DD15
0.25
—
SDCLK
DD16
0.4
0.6
SDCLK
SDCLK
SDCLK
V
IX
V
MP
V
IX
V
ID
相關PDF資料
PDF描述
MC68HC711E9xx APPENDIX A ELECTRICAL CHARACTERISTICS
MC68HCL05J1A TRANSISTOR,BJT,NPN,20V V(BR)CEO,400MA I(C),TO-39
MC9S12A256B device made up of standard HCS12 blocks and the HCS12 processor core
MC68HC811E2 APPENDIX A ELECTRICAL CHARACTERISTICS
MC68HC811E2C APPENDIX A ELECTRICAL CHARACTERISTICS
相關代理商/技術參數(shù)
參數(shù)描述
MCF547X_07 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire㈢ Microprocessor
MCF5480 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor
MCF5480CVR166 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5480CZP166 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5481 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*