參數(shù)資料
型號(hào)： MCF5407FT220
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 220 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁(yè)數(shù)： 9/35頁(yè)
文件大小： 441K
代理商： MCF5407FT220
MOTOROLA
MCF5407 Integrated ColdFire Microprocessor Product Brief
17
Programming Model, Addressing Modes, and Instruction Set
1.4.4.1
Addressing Capability Summary
The MCF5407 processor supports seven addressing modes (refer to Table 5). Register indirect addressing
modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling
data structures common to sophisticated embedded applications and high-level languages. The program
counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required
to support position-independent code. As part of the indexed addressing mode, ColdFire architecture
supports an optional scale factor that can be applied to the index register to easily access byte, word, or
longword entries within an array (x1, x2, x4).
An instruction’s effective addressing mode can specify the operand in one of three ways:
It can specify the data value directly as an immediate operand
It can specify the register containing the operand
It can specify the addressing calculation needed to reference the memory location containing the
operand
Each addressing mode has a unique assembler syntax. In addition to the generalized format where the
addressing mode is specified directly in the instruction, some opcodes implicitly define the effective
address. Table 5 summarizes supported effective addressing modes.
Subfields and Qualifiers
{}
Optional operation
()
Identifies an indirect address
dn
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
Address
Calculated effective address (pointer)
Bit
Bit selection (example: Bit 3 of D0)
lsb
Least significant bit (example: lsb of D0)
LSB
Least significant byte
LSW
Least significant word
msb
Most significant bit
MSB
Most significant byte
MSW
Most significant word
Condition Code Register Bit Names
C
Carry
N
Negative
VOverflow
X
Extend
ZZero
Table 4. Notational Conventions (continued)
Instruction
Operand Syntax
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