參數(shù)資料
型號： MCF5407FT220
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 220 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁數(shù)： 14/35頁
文件大?。?/td> 441K
代理商： MCF5407FT220
MOTOROLA
MCF5407 Integrated ColdFire Microprocessor Product Brief
21
Programming Model, Addressing Modes, and Instruction Set
describes supervisor-level instructions.
describes user-level instructions.
Table 9. Supervisor-Level Instruction Set Summary
Instruction
Operand Syntax
Operand Size
Operation
CPUSHL
(An)
Unsized
Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
HALT 1
1
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
none
Unsized
Enter halted state
INTOUCH
(Ax)
Unsized
Touch instruction space at address Ax
MOVE from SR
SR, Dx
.W
SR
→ Dx
MOVE to SR
Dy,SR
#<data>,SR
.W
Source
→ SR
MOVEC
Ry,Rc
.L
Ry
→ Rc
Rc
Register Definition
0x002
Cache control register (CACR)
0x004
Access control register 0 (ACR0)
0x005
Access control register 1 (ACR1)
0x006
Access control register 2 (ACR2)
0x007
Access control register 3 (ACR3)
0x801
Vector base register (VBR)
0xC04
RAM base address register 0 (RAMBAR0)
0xC05
RAM base address register 1 (RAMBAR1)
RTE
None
Unsized
(SP+2)
→ SR; SP+4 → SP; (SP) → PC; SP + formatfield SP
STOP
#<data>
.W
Immediate data
→ SR; enter stopped state
WDEBUG
<ea-2>y
.L
<ea-2>y
→ debug module
Table 10. User-Level Instruction Set Summary
Instruction
Operand Syntax
Operand Size
Operation
ADD
Dy,<ea>x
<ea>y,Dx
.L
Source + destination
→ destination
ADDA
<ea>y,Ax
.L
Source + destination
→ destination
ADDI
#<data>,Dx
.L
Immediate data + destination
→ destination
ADDQ
#<data>,<ea>x
.L
Immediate data + destination
→ destination
ADDX
Dy,Dx
.L
Source + destination + X
→ destination
AND
Dy,<ea>x
<ea>y,Dx
.L
Source & destination
→ destination
ANDI
#<data>,Dx
.L
Immediate data & destination
→ destination
ASL
Dy,Dx
#<data>,Dx
.L
X/C
← (Dx << Dy) ← 0
X/C
← (Dx << #<data>) ← 0
ASR
Dy,Dx
#<data>,Dx
.L
MSB
→ (Dx >> Dy) → X/C
MSB
→ (Dx >> #<data>) → X/C
Bcc
<label>
.B,.W,.L
If condition true, then PC + 2 + dn → PC
BCHG
Dy,<ea>x
#<data>,<ea-1>x
.B,.L
~(<bit number> of destination)
→ Z,
Bit of destination
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