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參數(shù)資料
| 型號： | MCF5407FT220 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 220 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208 |
| 文件頁數(shù)： | 33/35頁 |
| 文件大小： | 441K |
| 代理商： | MCF5407FT220 |
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MOTOROLA
MCF5407 Integrated ColdFire Microprocessor Product Brief
7
ColdFire Module Description
time stalled waiting for instructions. To maximize the performance of conditional branch instructions, the
Version 4 IFP implements a sophisticated two-level acceleration mechanism.
The first level is an 8-entry, direct-mapped branch cache with a 2-bit prediction state (strongly/weakly,
taken/not-taken) for each entry. The branch cache implements instruction folding techniques that allow
conditional branch instructions which are predicted correctly as taken to execute in zero cycles.
For those conditional branches with no information in the branch cache, a second-level, direct-mapped
prediction table containing 128 entries is accessed. Again, each entry uses the same 2-bit prediction state
definition as the branch cache. This branch prediction state is then used to predict the direction of prefetched
conditional branch instructions.
Other change-of-flow instructions, including unconditional branches, jumps, and subroutine calls, use a
similar mechanism where the IFP calculates the target address. The performance of subroutine return
instructions is improved through the use of a four-entry, LIFO return stack.
In all cases, these mechanisms allow the IFP to redirect the fetch stream down the path predicted to be taken
well in advance of the actual instruction execution. The net effect is significantly improved performance.
1.3.1.2
Operand Execution Pipeline (OEP)
The prefetched instruction stream is gated from the FIFO buffer into the five-stage OEP. The OEP consists
of two, traditional two-stage RISC compute engines with a register file access feeding an arithmetic/logic
unit (ALU). The compute engine located at the top of the OEP is typically used for operand memory address
calculations (the address ALU), while the compute engine located at the bottom of the pipeline is used for
instruction execution (the execution ALU). The resulting structure provides 3.9 Gbytes/S data operand
bandwidth at 162 MHz to the two compute engines and supports single-cycle execution speeds for most
instructions, including all load, store and most embedded-load operations. In response to users and
developers, the V4 design supports execution of the ColdFire Revision B instruction set, which adds a small
number of new instructions to improve performance and code density.
The OEP also implements two advanced performance features. It dynamically determines the appropriate
location of instruction execution (either in the address ALU or the execution ALU) based on the pipeline
state. The address compute engine, in conjunction with register renaming resources, can be used to execute
a number of heavily-used opcodes and forward the results to subsequent instructions without any pipeline
stalls. Additionally, the OEP implements instruction folding techniques involving MOVE instructions so
that two instructions can be issued in a single machine cycle. The resulting microarchitecture approaches
the performance of a full superscalar implementation, but at a much lower silicon cost.
1.3.1.3
MAC Module
The MAC unit provides signal processing capabilities for the MCF5407 in a variety of applications
including digital audio and servo control. Integrated as an execution unit in the processor's OEP, the MAC
unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input
operands are supported by this design in addition to a full set of extensions for signed and unsigned integers
plus signed, fixed-point fractional input operands.
1.3.1.4
Integer Divide Module
Some embedded applications can benefit greatly from the integer divide unit. Integrated as another engine
in the processor’s OEP, the divide module performs a variety of operations using signed and unsigned
integers. The module supports word and longword divides producing quotients and/or remainders.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MCF54410CMF250 | 制造商:Freescale Semiconductor 功能描述:MCF54410CMF250 - Bulk |
| MCF54415CMJ250 | 功能描述:微處理器 - MPU COLDFIREV4M CORE C90LP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF54415CMJ250 | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MCU COLDFIRE 250MHZ 256-MA |
| MCF54416CMJ250 | 功能描述:微處理器 - MPU COLDFIREV4M CORE C90LP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF54416CMJ250 | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU COLDFIRE 250MHZ 256-MA |
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