參數(shù)資料
型號: MCF5407
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: ColdFire Integrated Microprocessor(ColdFire微處理器)
中文描述: 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁數(shù): 6/24頁
文件大?。?/td> 296K
代理商: MCF5407
6
MCF5407 Integrated ColdFire¨ Microprocessor
ColdFire Module Description
On-chip PLL
Accepts various clock input (CLKIN) frequencies between 25 and 54 MHz
Supports core frequencies between 100 and 162 MHz
Supports low-power mode
Product offerings
257 Dhrystone MIPS at 162 MHz
Implemented in 0.22 μ, quad-layer-metal process technology with 1.8-V operation (3.3-V
compliant I/O pads)
208-pin plastic QFP package
0D70 C operating temperature
1.2.1 Process
The MCF5407 is manufactured in a 0.22-μ CMOS process with quad-layer-metal routing technology. This
process combines the high performance and low power needed for embedded system applications. Inputs
are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0.5 V to
GND - 0.5 V, with guaranteed TTL-level speciTcations.
1.3 ColdFire Module Description
The following sections provide overviews of the various modules incorporated in the MCF5407.
1.3.1 ColdFire Core
The Version 4 ColdFire core consists of two, independent and decoupled pipelines to maximize
performancethe instruction fetch pipeline (IFP) and the operand execution pipeline (OEP).
1.3.1.1 Instruction Fetch Pipeline (IFP)
The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the operand execution
pipeline (OEP). Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer,
the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the
time stalled waiting for instructions. To maximize the performance of conditional branch instructions, the
Version 4 IFP implements a sophisticated two-level acceleration mechanism.
The Trst level is an 8-entry, direct-mapped branch cache with a 2-bit prediction state (strongly/weakly,
taken/not-taken) for each entry. The branch cache implements instruction folding techniques that allow
conditional branch instructions which are predicted correctly as taken to execute in zero cycles.
For those conditional branches with no information in the branch cache, a second-level, direct-mapped
prediction table containing 128 entries is accessed. Again, each entry uses the same 2-bit prediction state
deTnition as the branch cache. This branch prediction state is then used to predict the direction of prefetched
conditional branch instructions.
Other change-of-ow instructions, including unconditional branches, jumps, and subroutine calls, use a
similar mechanism where the IFP calculates the target address. The performance of subroutine return
instructions is improved through the use of a four-entry, LIFO return stack.
In all cases, these mechanisms allow the IFP to redirect the fetch stream down the path predicted to be taken
well in advance of the actual instruction execution. The net effect is signiTcantly improved performance.
相關(guān)PDF資料
PDF描述
MCM101524 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
MCM101524B12 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
MCM101524B15 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
MCM101525 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
MCM101525B12 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
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