參數(shù)資料
型號(hào)： MCF5407
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： ColdFire Integrated Microprocessor(ColdFire微處理器)
中文描述： 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 11/24頁(yè)
文件大小： 296K
代理商： MCF5407
MCF5407 Integrated ColdFire¨ Microprocessor
11
Programming Model, Addressing Modes, and Instruction Set
The on-chip breakpoint resources include a total of 13 programmable registerstwo sets of address
registers (each with two 32-bit registers), two sets of data registers (each with a 32-bit data register plus 32-
bit data mask register), one 32-bit PC register plus a 32-bit PC mask register and three additional 32-bit PC
registers. These registers can be accessed through the dedicated debug serial communication channel, or
from the processor's supervisor mode programming model. The breakpoint registers can be conTgured to
generate triggers by combining the address, data and PC conditions in a variety of single or dual-level
deTnitions and the trigger event can be programmed to generate a processor halt, or initiate a debug interrupt
exception.
The MCF5407s new interrupt servicing options during emulator mode allow real-time critical interrupt
service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the Version 4 debug module has combined the processor status and debug data
outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus along with the PSTCLK output provide
execution status, captured operand data and branch target addresses deTning processor activity at one-half
the CPU's clock rate.
1.3.10 PLL Module
The MCF5407 PLL module is shown in Figure 3.
Figure 3. PLL Module
The PLL modules three modes of operation (reset, normal, and reduced power) are described as follows.
￥
Reset modeWhen RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO
from the MCF5407. The core:bus frequency ratio along with other MCF5407 conTguration
information are sampled during reset.
Normal modeIn normal mode, the input frequency programmed at reset is clock-multiplied to
provide the processor clock (PCLK).
Reduced-power modeIn reduced-power mode, the PCLK is disabled by executing a sequence
including programming a control bit in the system conTguration register (SCR) and then executing
the STOP instruction. Register contents are retained in reduced-power mode, so the system can be
reenabled quickly when an unmasked interrupt or reset is detected.
￥
￥
1.4 Programming Model, Addressing Modes, and
Instruction Set
The ColdFire programming model is separated into two privilege modessupervisor and user, which is
indicated by the S bit in the status register (SR). The processor identiTes a logical address by accessing
either the supervisor or user address space, which differentiates between supervisor and user modes.
PLL
CLKIN
RSTI
PSTCLK
(= PCLK/2)
Debug Module
÷2
DIVIDE[2:0]
RSTO
PCLK (to core)
BCLKO
CLKIN (to on-chip peripherals)
相關(guān)PDF資料
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MCM101524 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
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