參數(shù)資料
型號: MCF5407
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: ColdFire Integrated Microprocessor(ColdFire微處理器)
中文描述: 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁數(shù): 19/24頁
文件大?。?/td> 296K
代理商: MCF5407
MCF5407 Integrated ColdFire¨ Microprocessor
19
Programming Model, Addressing Modes, and Instruction Set
The following list summarizes new and enhanced instructions of Revision B ISA:
New instructions:
INTOUCH loads blocks of instructions to be locked in the instruction cache
MOV3Q.L moves 3-bit immediate data to destination location
MVS.{B,W} sign-extends the source operand and moves it to destination register
MVZ.{B,W} zero-Tlls the source operand and moves it to destination register
SATS.L updates bit 31 of destination register depending on CCR overow bit
TAS.B tests and set byte operand being addressed.
Enhancements to existing Revision A instructions:
Longword support for branch instructions (Bcc, BRA, BSR)
Byte and word support for compare instructions (CMP, CMPI)
Byte and longword support for MOVE.x where the source is of type #<data> and the destination
is of type d16(Ax); that is, move.b #<data>, d16(Ax)
Table 8 lists the new and enhanced instructions.
Table 9
describes supervisor-level instructions.
Table 8. ColdFire ISA B Extension Summary
Instruction
Mnemonic
Branch Always
bra.l
Branch Conditionally
bcc.l
Branch to Subroutine
bsr.l
Compare
cmp.{b,w}
Compare Immediate
cmpi.{b,w}
Instruction Fetch Touch
intouch
Move 3-Bit Data Quick
mov3q.l
Move Data Source to Destination
move.{b,w}
Move with Sign Extend
mvs.{b,w}
Move with Zero-Fill
mvz.{b,w}
Signed Saturate
sats.l
Test and Set an Operand
tas.b
Table 9. Supervisor-Level Instruction Set Summary
Instruction
Operand Syntax
Operand Size
Operation
CPUSHL
(An)
Unsized
Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
HALT
1
none
Unsized
Enter halted state
INTOUCH
(Ax)
Unsized
Touch instruction space at address Ax
MOVE from SR
SR, Dx
.W
SR
Dx
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MCM101524 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
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