參數(shù)資料
型號： MCF5372LCVM240
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 240 MHz, RISC PROCESSOR, PBGA196
封裝： 15 X 15 MM, ROHS COMPLIANT, MAPBGA-196
文件頁數(shù)： 17/46頁
文件大?。?/td> 922K
代理商： MCF5372LCVM240
MCF537x ColdFire Microprocessor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
24
DD8
Data and Data Mask Output Hold (DQS-->DQ) Relative to
DQS (DDR Write Mode)6
tDQDMI
1.0
—
ns
DD9
Input Data Skew Relative to DQS (Input Setup)7
tDVDQ
—1
ns
DD10
Input Data Hold Relative to DQS8
tDIDQ
0.25
× SD_CLK
+0.5ns
—ns
DD11 DQS falling edge from SDCLK rising (output hold time)
tDQLSDCH
0.5
—
ns
DD12 DQS input read preamble width
tDQRPRE
0.9
1.1
SD_CLK
DD13 DQS input read postamble width
tDQRPST
0.4
0.6
SD_CLK
DD14 DQS output write preamble width
tDQWPRE
0.25
SD_CLK
DD15 DQS output write postamble width
tDQWPST
0.4
0.6
SD_CLK
1 SD_CLK is one SDRAM clock in (ns).
2 Pulse width high plus pulse width low cannot exceed min and max clock period.
3 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
4 This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
5 The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.
6 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
7 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
8 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.
Table 11. DDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF53721CVM240,
MCF5372LCVM240,
MCF5373LCVM240
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相關代理商/技術參數(shù)
參數(shù)描述
MCF5372LCVM240J 功能描述:32位微控制器 - MCU V3CORE RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
MCF5373 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor
MCF5373_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor
MCF5373CAB180 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microprocessor Data Sheet
MCF5373L 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor
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