參數(shù)資料
型號(hào): MCF5372LCVM240
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 240 MHz, RISC PROCESSOR, PBGA196
封裝: 15 X 15 MM, ROHS COMPLIANT, MAPBGA-196
文件頁(yè)數(shù): 13/46頁(yè)
文件大小: 922K
代理商: MCF5372LCVM240
MCF537x ColdFire Microprocessor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
20
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
Figure 7. FlexBus Read Timing
FB4
Data Input Setup
tDVFBCH
3.5
ns
FB5
Data Input Hold
tDIFBCH
0—
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4—
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0—
ns
1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC
Timing Characteristics” for SD_CS[3:0] timing.
2 The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
Table 9. FlexBus AC Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
FB_CLK
FB_R/W
S0
S1
S2
S3
FB_TS
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
DATA
ADDR[31:X]
ADDR[23:0]
FB3
FB1
FB2
FB5
FB4
FB7
FB6
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF53721CVM240,
MCF5372LCVM240,
MCF5373LCVM240
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