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| 型號： | MCF5235CVM150 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | MAPBGA-256 |
| 文件頁數(shù)： | 50/76頁 |
| 文件大小： | 2665K |
| 代理商： | MCF5235CVM150 |
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54
MCF523x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Oscillator and PLLMRFM Electrical Characteristics
13
1:1 Mode Clock Skew (between CLKOUT
and EXTAL) 11
tskew
–1
1
ns
14
Duty Cycle of reference 5
tdc
40
60
%
15
Frequency un-LOCK Range
fUL
–3.8
4.1
% fsys/2
16
Frequency LOCK Range
fLCK
–1.7
2.0
% fsys/2
17
CLKOUT Period Jitter, 5, 6, 9, 12, 13
Measured at fsys/2 Max
Peak-to-peak Jitter (Clock edge to clock
edge)
Long Term Jitter (Averaged over 2 ms
interval)
Cjitter
—
5.0
.01
% fsys/2
18
Frequency Modulation Range Limit 14, 15
(fsys/2 Max must not be exceeded)
Cmod
0.8
2.2
%fsys/2
19
ICO Frequency. fico = fref * 2 * (MFD+2)
16
fico
48
75
MHz
1
All values given are initial design targets and subject to change.
2
All internal registers retain data at 0 Hz.
3
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL
into self clocked mode.
4
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency
falls below fLOR with default MFD/RFD settings.
5
This parameter is guaranteed by characterization before qualification rather than 100% tested.
6
Proper PC board layout procedures must be followed to achieve specifications.
7
This parameter is guaranteed by design rather than 100% tested.
8
This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).
9
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are
valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.
10 t
lpll = (64 * 4 * 5 + 5
× τ) × T
ref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10
-6
×
2(MFD + 2).
11 PLL is operating in 1:1 PLL mode.
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a
stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in
crystal oscillator frequency increase the Cjitter percentage for a given interval.
13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.
14 Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100KHz.
15 Modulation rate selected must not result in f
sys/2 value greater than the fsys/2 maximum specified value.
Modulation range determined by hardware design.
16 f
sys/2 = fico / (2 * 2
RFD)
Table 45. HiP7 PLLMRFM Electrical Specifications 1
Num
Characteristic
Symbol
Min.
Value
Max.
Value
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PDF描述 |
|---|---|
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| MCF5232CVM100 | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA196 |
| MCF5271CVM150 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA196 |
| MCF5270AB100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP160 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5235CVM150 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
| MCF5235CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5235CVM150J | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 150 MHz 256-BGA |
| MCF5235EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
| MCF523X | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
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