
MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
1.3.12 QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral interface
with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU
intervention between transfers.
1.3.13 Cryptography
The MCF5235 device incorporates small, fast, dedicated hardware accelerators for random number
generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions allowing for
the implementation of common Internet security protocol cryptography operations with performance well
in excess of software-only algorithms.
1.3.14 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the MCF523x. Each
timer module incorporates a 32-bit timer with a separate register set for configuration and control. The
timers can be configured to operate from the system clock or from an external clock source using one of the
DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided
by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these
timers can be configured for input capture or reference compare mode. By configuring the internal registers,
each timer may be configured to assert an external signal, generate an interrupt on a particular event or cause
a DMA transfer.
1.3.15 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular
intervals with minimal processor intervention. Each timer can either count down from the value written in
its PIT modulus register, or it can be a free-running down-counter.
1.3.16 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is
a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
1.3.17 Clock Module and Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider
(RFD), status/control registers, and control logic. To improve noise immunity, the PLL and OSC have their
own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins,
VDD and VSS.
1.3.18 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers on the MCF523x, each of which can support up to 63 interrupt sources
each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level.