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| 型號： | MCAQE16G6APP-MXA |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP |
| 封裝： | LQFP |
| 文件頁數(shù)： | 9/65頁 |
| 文件大小： | 799K |
| 代理商： | MCAQE16G6APP-MXA |
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NAND Flash-based Solid State Disk
17
Sep. 27. 2006
Figure 1 defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or
4 shall power-up in a PIO mode 0,1, or 2.
For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 1
defines the minimum value that shall be placed in word 68.
Both hosts and devices shall support IORDY when PIO mode 3 or 4 are the currently selected mode of operation.
DIOR-/DIOW-
WRITE DD(7:0)
READ DD(7:0)
IORDY
t1
ADDR valid
t2
(See note 1)
(See note 2)
(See note 3,3-2)
IORDY
(See note 3,3-1)
IORDY
(See note 3,3-3)
t9
t0
t3
t4
t5
t6
t6Z
tA
tC
tRD
tB
tC
NOTE:
1. Device address consists of signals CS0-, CS1- and DA(2:0)
2. Data consists of DD(7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made
by the host after tA from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases:
3-1. Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2. Device negates IORDY before tA, but causes IORDY to be asserted before tA.
IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.
3-3. Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated.
The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on
DD(7:0) for tRD before asserting IORDY.
4. DMACK- shall remain negated during a register transfer.
Figure 1. Register transfer to/from device.
t2i
4.5.1 Register Transfers
4.5 AC Characteristics
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