參數(shù)資料
型號： MC9328MXLCVP15
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 微處理器
英文描述： i.MX Integrated Portable System Processor
中文描述： i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù)： 28/96頁
文件大?。?/td> 1495K
代理商： MC9328MXLCVP15
MC9328MX1 Advance Information, Rev. 4
28
Freescale Semiconductor
Specifications
3.9.2.4 DTACK Write Cycle DMA Enabled
Figure 9. DTACK Write Cycle DMA Enabled
Note
:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB
assertion can also be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5
pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T+0.58
1.5T+1.58
ns
5
Address inactive before CS negated
–
0.93
ns
6
DTACK
asserted after CS5 asserted
–
1019T
ns
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
OE
DTACK
Address
EB
CS5
RW
(logic high)
Databus
output from MX1)
programmable
min 0ns
programmable
min 0ns
(1)
(2)
(7)
(8)
(4)
(5)
(3)
(6)
(9)
(10)
(11)
(12)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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