參數(shù)資料
型號(hào)： MC9328MXLCVP15
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類(lèi)： 微處理器
英文描述： i.MX Integrated Portable System Processor
中文描述： i.MX處理器集成的便攜式系統(tǒng)
文件頁(yè)數(shù)： 19/96頁(yè)
文件大?。?/td> 1495K
代理商： MC9328MXLCVP15
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
19
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, T
ref
is a reference clock period after the pre-divider
and T
dck
is the output double clock period.
Table 11. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock freq range
Vcc = 1.8V
5
–
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
–
30
MHz
Double clock freq range
Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor
(MF)
Includes both integer
and fractional parts
5
–
15
–
MF
integer part
–
5
–
15
–
MF
numerator
Should be less than the
denominator
0
–
1022
–
MF
denominator
–
1
–
1023
–
Pre-multiplier lock-in time
–
–
–
312.5
μ
sec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-must lock-in time)
250
280
(56
μ
s)
300
T
ref
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
220
250
(~50
μ
s)
270
T
ref
Phase lock-in time after
full reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
300
350
(70
μ
s)
400
T
ref
Phase lock-in time after
partial reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
270
320
(64
μ
s)
370
T
ref
Freq jitter (p-p)
–
–
0.005
(0.01%)
0.01
2T
dck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
1.5
ns
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
f
dck
= 200 MHz, Vcc = 1.8V
–
–
4
mW
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MXLCVP15 制造商:Freescale Semiconductor 功能描述:Microprocessor
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