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參數(shù)資料
| 型號： | MC9328MX21CVM |
| 廠商： | Motorola, Inc. |
| 英文描述： | i.MX family of microprocessors |
| 中文描述： | i.MX系列微處理器 |
| 文件頁數(shù)： | 6/96頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | MC9328MX21CVM |
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MC9328MX1 Advance Information, Rev. 4
6
Freescale Semiconductor
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [24:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16]
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8]
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]
OE
Memory Output Enable—Active low output enables external data bus
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by
the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on
SDRAM/SyncFlash cycles.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21CVM | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21CVMR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVG | 制造商:Rochester Electronics LLC 功能描述:DB I.MX21 - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9328MX21DVH | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:i.MX family of microprocessors |
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