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參數(shù)資料
| 型號(hào)： | MC9328MX21CVM |
| 廠商： | Motorola, Inc. |
| 英文描述： | i.MX family of microprocessors |
| 中文描述： | i.MX系列微處理器 |
| 文件頁(yè)數(shù)： | 25/96頁(yè) |
| 文件大?。?/td> | 1495K |
| 代理商： | MC9328MX21CVM |
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Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
25
3.9.2.2 DTACK Read Cycle DMA Enabled
Figure 7. DTACK Read Cycle DMA Enabled
5
DTACK
asserted to OE negated
3T+2.2
4T+6.86
ns
6
Data hold timing after OE negated
0
–
ns
7
Data ready after DTACK
asserted
0
T
ns
8
OE negated to CS negated
0.5T+0.24
0.5T+0.67
ns
9
OE negated after EB negated
0.5
1.5
ns
10
DTACK
pulse width
1T
3T
ns
Note
:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB
assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
RW
DTACK
Address
EB
CS5
OE
(logic high)
Databus
input to MX1)
programmable
min 0ns
(1)
(6)
(7)
(3)
(4)
(2)
(5)
(8)
(9)
(10)
(11)
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| MC9328MX21CVM | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21CVMR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVG | 制造商:Rochester Electronics LLC 功能描述:DB I.MX21 - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9328MX21DVH | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:i.MX family of microprocessors |
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