
Slave LIN Interface Controller (SLIC) Module
MC68HC908QL4  MC68HC908QL3  MC68HC908QL2 Data Sheet, Rev. 4
140
Freescale Semiconductor
IMSG — SLIC Ignore Message Bit
IMSG cannot be cleared by a write of 0, but is cleared automatically by the SLIC module after the next 
BREAK/SYNC symbol pair is validated. After it is set, IMSG will not keep data from being written to the 
receive data buffer, which means that the buffers cannot be assumed to contain known valid message 
data until the next receive buffer full interrupt. IMSG must not be used in BTM mode.
1 = SLIC to ignore data field of message, SLIC interrupts are suppressed until the next message 
header arrives 
0 = Normal operation
SLCIE — SLIC Interrupt Enable
1 = SLIC interrupt sources are enabled 
0 = SLIC interrupt sources are disabled 
14.8.2  SLIC Control Register 2
SLIC control register 2 (SLCC2) contains bits used to control various features of the SLIC module.
SLCWCM — SLIC Wait Clock Mode
This bit can only be written once out of reset state.
1 = SLIC clocks stop when the CPU is placed into wait mode
0 = SLIC clocks continue to run when the CPU is placed into wait mode so that the SLIC can receive 
messages and wakeup the CPU.
BTM — UART Byte Transfer Mode
Byte transmit mode bypasses the normal LIN message framing and checksum monitoring and allows 
the user to send and receive single bytes in a method similar to a half-duplex UART. When enabled, 
this mode reads the bit time register (SLCBT) value and assumes this is the value corresponding to 
the number of SLIC clock counts for one bit time to establish the desired UART bit rate. The user 
software must initialize this register prior to sending or receiving data, based on the input clock 
selection, prescaler stage choice, and desired bit rate.
BTM forces the data length in SLCDLC to one byte (DLC = 0x00) and disables the checksum circuitry 
so that CHKMOD has no effect. Refer to 
14.9.15 Byte Transfer Mode Operation
 for more detailed 
information about how to use this mode. BTM sets up the SLIC module to send and receive one byte 
at a time, with 8-bit data, no parity, and one stop bit (8-N-1). This is the most commonly used setup for 
UART communications and should work for most applications. This is fixed in the SLIC and is not 
configurable. 
1 = UART byte transfer mode enabled
0 = UART byte transfer mode disabled 
SLCE — SLIC Module Enable
1 = SLIC module enabled
0 = SLIC module disabled
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
SLCWCM
BTM
0
SLCE
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-5. SLIC Control Register 2 (SLCC2)