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參數資料
| 型號： | MC8641VU1333JE |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 123/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU SGL CORE E600 1023FCCBGA |
| 標準包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 994-BCBGA，F(xiàn)CCBGA |
| 供應商設備封裝： | 994-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
92
Freescale Semiconductor
Signal Listings
NOTES for Figure 58
1.
All dimensions are in millimeters.
2.
Dimensions and tolerances per ASME Y14.5M-1994.
3.
Maximum solder ball diameter measured parallel to datum A.
4.
Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
5.
Capacitors may not be present on all devices.
6.
Caution must be taken not to short capacitors or expose metal capacitor pads on package top.
7.
All dimensions symmetrical about centerlines unless otherwise specified.
8.
Note that for MPC8641 (single core) the solder balls for the following signals/pins are not populated in the package:
VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17,
Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).
17 Signal Listings
Table 63 provides the pin assignments for the signals. Notes for the signal changes on the single core
device (MPC8641) are italicized and prefixed by “S”.
Table 63. MPC8641 Signal Reference by Functional Block
Name1
Package Pin Number
Pin Type
Power Supply
Notes
DDR Memory Interface 1 Signals2,3
D1_MDQ[0:63]
D15, A14, B12, D12, A15, B15, B13, C13,
C11, D11, D9, A8, A12, A11, A9, B9, F11,
G12, K11, K12, E10, E9, J11, J10, G8, H10,
L9, L7, F10, G9, K9, K8, AC6, AC7, AG8,
AH9, AB6, AB8, AE9, AF9, AL8, AM8,
AM10, AK11, AH8, AK8, AJ10, AK10, AL12,
AJ12, AL14, AM14, AL11, AM11, AM13,
AK14, AM15, AJ16, AK18, AL18, AJ15,
AL15, AL17, AM17
I/O
D1_GVDD
—
D1_MECC[0:7]
M8, M7, R8, T10, L11, L10, P9, R10
I/O
D1_GVDD
—
D1_MDM[0:8]
C14, A10, G11, H9, AD7, AJ9, AM12, AK16,
N10
O
D1_GVDD
—
D1_MDQS[0:8]
A13, C10, H12, J7, AE8, AM9, AK13, AK17,
N9
I/O
D1_GVDD
—
D1_MDQS[0:8]
D14, B10, H13, J8, AD8, AL9, AJ13, AM16,
P10
I/O
D1_GVDD
—
D1_MBA[0:2]
AA8, AA10, T9
O
D1_GVDD
—
D1_MA[0:15]
Y10, W8, W9, V7, V8, U6, V10, U9, U7, U10,
Y9, T6, T8, AE12, R7, P6
O
D1_GVDD
—
D1_MWE
AB11
O
D1_GVDD
—
D1_MRAS
AB12
O
D1_GVDD
—
D1_MCAS
AC10
D1_GVDD
—
D1_MCS[0:3]
AB9, AD10, AC12, AD11
O
D1_GVDD
—
D1_MCKE[0:3]
P7, M10, N8, M11
O
D1_GVDD
23
D1_MCK[0:5]
W6, E13, AH11, Y7, F14, AG10
O
D1_GVDD
—
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