參數(shù)資料
型號: MC8641HX1250HC
廠商: Freescale Semiconductor
文件頁數(shù): 102/130頁
文件大?。?/td> 0K
描述: IC MPU SGL E600 CORE 994FCCBGA
標準包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.25GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 994-BCBGA,F(xiàn)CCBGA
供應商設備封裝: 994-FCCBGA(33x33)
包裝: 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
73
PCI Express
14.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see
Figure 52) in place of any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications
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