參數(shù)資料
型號: MC860SRCZQ50D4R2
廠商: Freescale Semiconductor
文件頁數(shù): 53/78頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 50MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
Freescale Semiconductor
57
CPM Electrical Characteristics
Figure 58. HDLC Bus Timing Diagram
11.8
Ethernet Electrical Specifications
Table 22 provides the Ethernet timings as shown in Figure 59 through Figure 63.
Table 22. Ethernet Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
120
CLSN width high
40
ns
121
RCLK1 rise/fall time
15
ns
122
RCLK1 width low
40
ns
123
RCLK1 clock period1
80
120
ns
124
RXD1 setup time
20
ns
125
RXD1 hold time
5
ns
126
RENA active delay (from RCLK1 rising edge of the last data bit)
10
ns
127
RENA width low
100
ns
128
TCLK1 rise/fall time
15
ns
129
TCLK1 width low
40
ns
130
TCLK1 clock period1
99
101
ns
131
TXD1 active delay (from TCLK1 rising edge)
10
50
ns
132
TXD1 inactive delay (from TCLK1 rising edge)
10
50
ns
133
TENA active delay (from TCLK1 rising edge)
10
50
ns
134
TENA inactive delay (from TCLK1 rising edge)
10
50
ns
TCLK1
CTS1
(Echo Input)
102
100
104
TxD1
(Output)
102
101
RTS1
(Output)
103
104
107
105
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