參數(shù)資料
型號(hào)： MC80C52XXX-20SHXXX
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40
封裝： 0.600 INCH, SIDE BRAZED, DIP-40
文件頁數(shù)： 38/134頁
文件大?。?/td> 3805K
代理商： MC80C52XXX-20SHXXX
132
8011Q–AVR–02/2013
ATmega164P/324P/644P
Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O/8)
13.11 Register Description
13.11.1
TCCR1A – Timer/Counter1 Control Register A
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting. Table 13-2 on page 132 shows the COMnx1:0 bit functionality
when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
TOVn(FPWM)
and ICF n(if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
5
4
3210
COM1A1
COM1A0
COM1B1
COM1B0
–
WGM11
WGM10
TCCR1A
Read/Write
R/W
R
R/W
Initial Value
0
0000
Table 13-2.
Compare Output Mode, non-PWM
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
Normal port operation, OCnA/OCnB disconnected.
0
1
Toggle OCnA/OCnB on Compare Match.
10
Clear OCnA/OCnB on Compare Match (Set output to
low level).
11
Set OCnA/OCnB on Compare Match (Set output to
high level).
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