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參數(shù)資料
| 型號： | MC7457VG867NC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 50/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 867MHZ 483FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 483-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 483-FCCBGA（29x29） |
| 包裝： | 托盤 |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
System Design Information
Freescale Semiconductor
54
9.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7457 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown
in Figure 24 using surface mount capacitors with minimum effective series inductance (ESL) is
recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias.
Figure 24. PLL Power Supply Filter Circuit
NOTE
All production 7447 and 7457 Rev. B devices require a 400
Ω resistor
instead of the 10
Ω resistor shown above. All production 7457 Rev. C
devices require a 10
Ω resistor. For more information, see the MPC7450
Family Chip Errata for the MPC7457 and MPC7447.
9.3
Decoupling Recommendations
Due to the MPC7457 dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC7457 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one decoupling
capacitor at each VDD, OVDD, and GVDD pin of the MPC7457. It is also recommended that these
decoupling capacitors receive their power from separate VDD, OVDD/GVDD, and GND power planes in
the PCB, utilizing short traces to minimize inductance. If compromises must be made due to board
constraints, VDD pins should receive the highest priority for decoupling.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to
previous recommendations for decoupling Freescale microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick
VDD
AVDD
10
Ω
2.2 F
GND
Low ESL Surface Mount Capacitors
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