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參數(shù)資料
| 型號(hào)： | MC7457VG867NC |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 21/71頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU RISC 867MHZ 483FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 483-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 483-FCCBGA（29x29） |
| 包裝： | 托盤(pán) |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Electrical and Thermal Characteristics
Freescale Semiconductor
28
L3_CLK to high impedance: All
other outputs
tL3CHOZ
—(tL3CLK/4)
+ 0.65
—(tL3CLK/4)
+ 0.65
ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
or falling edge of the input L3_ECHO_CLK
n (see Figure 10). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLK
n as shown in Figure 10. For consistency with other
input setup time specifications, this will be treated as negative input setup time.
4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the MPC7457 can latch an input signal that is
valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges
of L3_ECHO_CLK
n at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of
L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a
purely resistive 50-
Ω load (see Figure 8).
6. For DDR, the output data will typically lead the edge of L3_CLK
n as shown in Figure 10. For consistency with other output
valid time specifications, this will be treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
8. Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for more
information.
9. L3 I/O voltage mode must be configured by L3VSEL as described in Table 3, and voltage supplied at GVDD must match mode
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
Device Revision (L3 I/O Voltage) 9
Unit
Notes
Rev 1.1. (All I/O Modes)
Rev 1.2 (1.5-V I/O Mode)
Rev 1.2
(1.8-, 2.5-V I/O Modes)
Min
Max
Min
Max
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