參數(shù)資料
型號： MC7447RX867LB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 867 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù)： 9/72頁
文件大?。?/td> 1598K
代理商： MC7447RX867LB
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7457 as defined in Figure 4 and
Figure 5. Timing specifications for the L3 bus are provided in Section 5.2.3, “L3 Clock AC
Internal PLL relock time
—100
μs7
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4]
settings.
2. Assumes lightly-loaded, single-processor system; see Section 5.2.1, “Clock AC Specifications” for more information.
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
867 MHz
1000 MHz
1200 MHz
1267 MHz
Min
Max
Min
Max
Min
Max
Min
Max
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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