參數(shù)資料
型號(hào)： MC7447RX867LB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 867 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 18/72頁(yè)
文件大?。?/td> 1598K
代理商： MC7447RX867LB
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Freescale Semiconductor
25
Electrical and Thermal Characteristics
5.2.4.2
L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9.
Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to
SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock
output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid
times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period
before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,
data, and L3_CLKn signals have propagated across the printed-wiring board.
Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2
SRAMs. These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal
circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data
L3CLKn_OH
All signals latched by
SRAM connected to
L3_CLKn
0b000
tL3CHOV,
tL3CHDV,
tL3CLDV
0tL3CHOX,
tL3CHDX,
tL3CLDX
0ps
4
0b001
– 50
5
0b010
– 100
5
0b011
– 150
5
0b100
– 200
5
0b101
– 250
5
0b110
– 300
5
0b111
– 350
5
L3DOHn
L3_DATA[n:n+7],
L3_DP[n/8]
0b000
tL3CHDV,
tL3CLDV
0tL3CHDX,
tL3CLDX
0ps
4
0b001
+ 50
0b010
+ 100
0b011
+ 150
0b100
+ 200
0b101
+ 250
0b111
+ 300
0b111
+ 350
Notes:
1. See the MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
2. See Table 13 and Table 14 for more information.
3. Approximate delay verified by simulation; not tested or characterized.
4. Default value.
5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of
all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing (continued)
At recommended operating conditions. See Table 4.
Field Name1
Affected Signals
Value
Output Valid Time
Output Hold Time
Unit
Notes
Parameter
Symbol 2
Change 3
Parameter
Symbol 2
Change 3
相關(guān)PDF資料
PDF描述
MC7448VS1267NC 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360
MC7448VU1400NC 32-BIT, 1400 MHz, RISC PROCESSOR, CBGA360
MC7448HX600NC 32-BIT, 600 MHz, RISC PROCESSOR, CBGA360
MC7448VU1400ND 32-BIT, 1400 MHz, RISC PROCESSOR, CBGA360
MC7448VU1267ND 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC7447RX867NB 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PPC7457RX1000NB
MC7448HX1000LC 功能描述:IC MPU RISC 32BIT 360-FCCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC74xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤
MC7448HX1000LD 功能描述:微處理器 - MPU APL8 RV2.2.1 1.15V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC7448HX1000N 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC7448 Hardware Specifications
MC7448HX1000NC 功能描述:IC MPU RISC 32BIT 360-FCCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC74xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*