參數(shù)資料
型號(hào)： MC7447AVU867NB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 31/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU RISC 32BIT 360-BGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類(lèi)型： 32-位 MPC74xx PowerPC
速度： 867MHz
電壓： 1.1V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 360-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤(pán)
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
37
System Design Information
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated core or bus frequency should avoid violating the stated limits by using
down-spreading only.
9.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7447A to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. A circuit similar to the one shown
in Figure 17 using surface-mount capacitors with minimum effective series inductance (ESL) is
recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the 360 HCTE footprint.
Figure 17. PLL Power Supply Filter Circuit
9.3
Decoupling Recommendations
Due to the MPC7447A dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC7447A can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC7447A system, and the MPC7447A itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer use sufficient decoupling
capacitors, typically one capacitor for every 1–2 VDD pins, and a similar or lesser number for the OVDD
pins, placed as close as possible to the power pins of the MPC7447A. It is also recommended that these
decoupling capacitors receive their power from separate VDD, OVDD, and GND power planes in the PCB,
utilizing short traces to minimize inductance.
Table 14. Spread Specturm Clock Source Recommendations
At recommended operating conditions. See Table 4.
Parameter
Min
Max
Unit
Notes
Frequency modulation
—
50
kHz
1
Frequency spread
—
1.0
%
1, 2
Notes:
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO
frequencies, must meet the minimum and maximum specifications given in Table 8.
VDD
AVDD
10
Ω
2.2 F
GND
Low ESL Surface Mount Capacitors
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