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| 型號： | MC7447AVU867NB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 32BIT 360-BGA |
| 標準包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-BCBGA，F(xiàn)CCBGA |
| 供應商設(shè)備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
11
Electrical and Thermal Characteristics
Table 4 provides the recommended operating conditions for the MPC7447A.
NOTE
Table 4 describes the nominal operating conditions of the device. For
information regarding the operation of the device at supported derated core
voltage conditions, see Section 5.3, “Voltage and Frequency Derating.”
Table 5 provides the package thermal characteristics for the MPC7447A.
Table 3. Input Threshold Voltage Settings
BVSEL Signal
Processor Bus Input Threshold is Relative to:
Notes
0
1.8 V
1, 2
HRESET
Not available
1
HRESET
2.5 V
1
12.5 V
1
Notes:
1. Caution: The input threshold selection must agree with the OVDD voltages supplied. See notes in Table 2.
2. If used, pull-down resistors should be less than 250
Ω.
Table 4. Recommended Operating Conditions1
Characteristic
Symbol
Recommended Value
Unit
Notes
Minimum
Maximum
Core supply voltage
VDD
1.3 V ± 50 mV
V
3
PLL supply voltage
AVDD
1.3 V ± 50 mV
V
2, 3
Processor bus supply voltage
BVSEL = 0
OVDD
1.8 V ± 5%
V
BVSEL = HRESET or OVDD
OVDD
2.5 V ± 5%
Input voltage
Processor bus
Vin
GND
OVDD
V
JTAG signals
Vin
GND
OVDD
Die-junction temperature
Tj
0105
°C
Notes:
1. These are the recommended and tested operating conditions. In addition, these devices also support voltage
derating; see Section 5.3, “Voltage and Frequency Derating.” Proper device operation outside of these conditions
and those specified in Section 5.3 is not guaranteed.
2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the
voltage at the AVDD pin, which may be reduced from VDD by the filter.
3. VDD and AVDD may be reduced in order to reduce power consumption if further maximum core frequency
constraints are observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information.
Table 5. Package Thermal Characteristics1
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board
RθJA
26
°C/W
2, 3
Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board
RθJMA
19
°C/W
2, 4
Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board
RθJMA
20
°C/W
2, 4
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