參數(shù)資料
型號: MC705P6ACDWE
廠商: Freescale Semiconductor
文件頁數(shù): 49/98頁
文件大小: 0K
描述: IC MCU 176 BYTES RAM 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 4.5KB(4.5K x 8)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
53
Chapter 9
Analog Subsystem
9.1 Introduction
The MC68HC705P6A includes a 4-channel, multiplexed input, 8-bit, successive approximation
analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port C pins PC3–PC7.
9.2 Analog Section
The following paragraphs describe the operation and performance of analog modules within the analog
subsystem.
9.2.1 Ratiometric Conversion
The A/D converter is ratiometric, with pin VREFH supplying the high reference voltage. Applying an input
voltage equal to VREFH produces a conversion result of $FF (full scale). Applying an input voltage equal
to VSS produces a conversion result of $00. An input voltage greater than VREFH will convert to $FF with
no overflow indication. For ratiometric conversions, VREFH should be at the same potential as the supply
voltage being used by the analog signal being measured and referenced to VSS.
9.2.2 Reference Voltage (V
REFH
)
The reference supply for the A/D converter shares pin PC7 with port C. The low reference is tied to the
VSS pin internally. VREFH can be any voltage between VSS and VDD; however, the accuracy of
conversions is tested and guaranteed only for VREFH = VDD.
9.2.3 Accuracy and Precision
The 8-bit conversion result is accurate to within
±1 1/2 LSB, including quantization; however, the accuracy
of conversions is tested and guaranteed only with external oscillator operation.
9.3 Conversion Process
The A/D reference inputs are applied to a precision digital-to-analog converter. Control logic drives the
D/A and the analog output is successively compared to the selected analog input which was sampled at
the beginning of the conversion cycle. The conversion process is monotonic and has no missing codes.
9.4 Digital Section
The following paragraphs describe the operation and performance of digital modules within the analog
subsystem.
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