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參數(shù)資料
| 型號： | MC68LC302PU20CT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 57/128頁 |
| 文件大小： | 641K |
| 代理商： | MC68LC302PU20CT |
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MC68EN302 DRAM Control Module
MOTOROLA
MC68EN302 REFERENCE MANUAL
3-3
Bits 15–8—Reserved. Should be written to zero by the host processor. These bits are
always read as zero.
R7-R0—Refresh Count Bits. The value stored in these bits is multiplied by 16 system clocks
to determine the refresh period. The divide by 16 scheme provides sufficient range to
address systems operating with standard DRAM at frequencies less than 2 Mhz as well as
systems utilizing low power DRAM running at frequencies greater than 25 Mhz. All zeroes
correspond to 4096 system clocks.
3.5 DRAM BASE ADDRESS REGISTER (DBA1-DBA0)
The base address registers for DRAM are two 16-bit registers which are initialized to zero
at hardware reset. These registers hold both the base address of each bank and mask bits
for determining which address bits initiate bus cycle accesses to the DRAM banks.
A23-A17—Base Address Bits. The Base Address Bits determine where the DRAM bank is
located on 128 kbyte boundaries. These bits are compared with the corresponding
addresses generated by the MC68EN302 to determine if a given bus cycle accesses a
particular DRAM bank. These bits are used in conjunction with the Mask Bits to determine
the size and location of a given DRAM bank.
Bits 8–7—Reserved. Should be written to zero by the host processor. These bits are always
read as zero.
M22-17—Mask Bits. These bits are used in conjunction with the Base Address Bits to
determine the size and location of a given DRAM bank.
0 = The corresponding address bit is ignored.
1 = The address compare logic uses the corresponding address bit when determining
if a bus cycle access occurs within the DRAM bank.
V—Valid Bit. This bit is cleared to 0 at hardware reset.
0 = This DRAM bank is not valid
1 = Data for the corresponding DRAM bank data is valid, and DRAM accesses are
decoded by that bank’s circuitry.
3.6 DRAM CONTROL MODULE OPERATION
3.6.1 Reset Operation
Refresh accesses continue if the Ethernet module is reset and during the Reset Instruction
(soft reset), but not during system (hardware) reset.
15
14
13
12
11
10
9876543210
A23
A22
A21
A20
A19
A18
A17
0
M22
M21
M20
M19
M18
M17
V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68LC302PU20VCT | 功能描述:IC MPU NETWORK 20MHZ 100-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68LC302PU25CT | 功能描述:微處理器 - MPU 25MHz 2.5MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LK332ACAG16 | 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MC68LK332ACAG16 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
| MC68LK332ACEH16 | 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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