- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45216 > MC68LC302PU20CT (MOTOROLA INC) 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | MC68LC302PU20CT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 104/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | MC68LC302PU20CT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁當(dāng)前第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Signal Descriptions
5-10
MC68EN302 REFERENCE MANUAL
MOTOROLA
The MC68EN302 DISCPU state is sampled during hardware reset just as in the MC68302.
The M68000 core is disabled by asserting the DISCPU pin high during total system reset.
5.5.15 PARITY1/BUSW
Parity is controlled by the PCSR Register in the module bus controller. This bidirectional pin
provides even or odd parity for byte 1 (bit 7–bit 0) when not in the reset state.
The state of BUSW is sampled during total system reset. When the BUSW is low during
hardware reset, it does not put the 68000 into 68008 mode with an 8 bit bus. Instead, having
the BUSW low during hardware reset will force the four EN8 bits in the CSER registers to
one, enabling support for dynamic bus sizing in the chip selects. Note that because the
68000 core is in normal 16 bit mode, if the 68000 accesses memory outside of the four chip
select areas, it always performs a normal 16 bit access.
5.5.16 PARITYE/THREESTATE
During normal operation, this bidirectional pin is the active low PARITYE (parity error)
output, and is asserted whenever one of the PED (Parity Error DRAM) bits in the PCSR is
asserted.
If this pin is low during total system reset, all bidirectional pins and output pins will be put
into three-state mode. This is intended for chip test purposes.
5.6 DRAM CONTROLLER I/O
5.6.1 Control Signal Pins
The EN302 contains 8 DRAM specific signal pins: CAS1–CAS0, RAS1–RAS0, AMUX, and
DRAMRW.
5.6.2 Column Address Strobes (CAS1–CAS0)
These active low pins allow seamless interface to Column Address Strobe (CAS) inputs on
industry standard DRAM, providing CAS for both bank 0 and bank 1 of the DRAM controller.
Two strobes support byte operations on the external 16-bit bus. CAS0 corresponds to data
pins D15-D8. CAS1 corresponds to data pins D7–D0.
5.6.3 Row Address Strobes (RAS1–RAS0)
These active low pins allow seamless interface to Row Address Strobe (RAS) inputs on
industry standard DRAM, providing RAS for both bytes of a given DRAM bank. A particular
bank corresponds to specific Base Address and Control information programmed in the
MC68EN302 DRAM control registers (see 3.2 Memory Map for a description). RAS0
corresponds to bank 0 and RAS1 corresponds to Bank 1.
5.6.4 DRAM Read/Write (DRAMRW)
This active low pin is asserted to signify that a DRAM write cycle is occurring. It is separate
from the processor bus R/W so that precharge takes place without regard to the state of R/
W.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68EN302PV25BT | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| MC68302PV33C | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| SPAK302PV16VC | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| SPAK302FC25C | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| MC68EN360EM25 | 7 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68LC302PU20VCT | 功能描述:IC MPU NETWORK 20MHZ 100-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68LC302PU25CT | 功能描述:微處理器 - MPU 25MHz 2.5MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LK332ACAG16 | 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MC68LK332ACAG16 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
| MC68LK332ACEH16 | 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。