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參數(shù)資料
| 型號： | MC68L11FC0PU3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, MICROCONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 50/74頁 |
| 文件大小： | 513K |
| 代理商： | MC68L11FC0PU3 |
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MOTOROLA
MC68HC11F1/FC0
54
MC68HC11FTS/D
11.1 Input Pins
Port E pins can also be used as digital inputs. Reads of port E pins are not recommended during the
sample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is on. Be-
cause no P-channel devices are directly connected to either input pins or reference voltage pins, volt-
ages above VDD do not cause a latchup problem, although current should be limited according to
maximum ratings. Figure 15 is a functional diagram of an input pin.
Figure 15 Electrical Model of an Analog Input Pin (Sample Mode)
11.2 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can be repeated continuously or stop after one iteration. The conversion complete flag (CCF) is set after
the fourth conversion in a sequence to show the availability of data in the result registers. Figure 16
shows the timing of a typical sequence. Synchronization is referenced to the system E clock.
Figure 16 A/D Conversion Sequence
DIFFUSION/POLY
< 2 pF
COUPLER
400 nA
JUNCTION
LEAKAGE
+ ~20V
– ~0.7V
*
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
VRL
INPUT
+ ~12V
– ~0.7V
PROTECTION
DEVICE
≤ 4 K
DUMMY N-CHANNEL
OUTPUT DEVICE
ANALOG
INPUT
PIN
~ 20 pF
DAC
CAPACITANCE
0
32
64
96
128 — E CYCLES
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
MSB
4
CYCLES
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
2
CYC
END
REPEAT
SEQUENCE,
SCAN
=
1
SET
CC
FLAG
CONVERT FIRST
CHANNEL, UPDATE
ADR1
CONVERT SECOND
CHANNEL, UPDATE
ADR2
CONVERT THIRD
CHANNEL, UPDATE
ADR3
CONVERT FOURTH
CHANNEL, UPDATE
ADR4
12 E CYCLES
WRITE
TO
ADCTL
E CLOCK
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