參數(shù)資料
型號(hào)： MC68L11FC0PU3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： Technical Summary 8-Bit Microcontroller
中文描述： 8-BIT, MICROCONTROLLER, PQFP80
封裝： TQFP-80
文件頁(yè)數(shù)： 20/74頁(yè)
文件大小： 513K
代理商： MC68L11FC0PU3
MC68HC11F1/FC0
MOTOROLA
MC68HC11FTS/D
27
CR[1:0] — COP Timer Rate Select
The COP system is driven by a constant frequency of E/215. CR[1:0] specify an additional divide-by fac-
tor to arrive at the COP time-out rate.
Write $55 to COPRST to arm the COP watchdog clearing mechanism. Then write $AA to COPRST to
reset the COP timer. Performing instructions between these two steps is possible provided both steps
are completed in the correct sequence before the timer times out.
PSEL[3:0] — Interrupt Priority Select Bits
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to have priority over other I-bit related sources.
Table 12 COP Watchdog Time-Out Periods
Frequency
Tolerance
CR[1:0] = 00
CR[1:0] = 01
CR[1:0] = 10
CR[1:0] = 11
1 MHz
-0/+32.768 ms
32.768 ms
131.072 ms
524.288 ms
2.097 s
2 MHz
-0/+16.384 ms
16.384 ms
65.536 ms
262.144 ms
1.049 s
3 MHz
-0/+10.923 ms
10.923 ms
43.691 ms
174.763 ms
699.051 ms
4 MHz
-0/+8.192 ms
8.192 ms
32.768 ms
131.072 ms
524.288 ms
5 MHz
-0/+6.554 ms
6.554 ms
26.214 ms
104.858 ms
419.430 ms
6 MHz
-0/+5.461 ms
5.461 ms
21.845
87.381 ms
349.525 ms
Any E
-0/+215/E
215/E
217/E
219/E
221/E
COPRST — Arm/Reset COP Timer Circuitry
$x03A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$x03C
Bit 7
654321
Bit 0
RBOOT
SMOD
MDA
IRV
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
0101
Table 13 Highest Priority Interrupt Selection
PSEL[3:0]
Interrupt Source Promoted
0000
Timer Overflow
0001
Pulse Accumulator Overflow
0010
Pulse Accumulator Input Edge
0011
SPI Serial Transfer Complete
0100
SCI Serial System
0101
Reserved (Default to IRQ)
0110
IRQ (External Pin)
0111
Real-Time Interrupt
1000
Timer Input Capture 1
1001
Timer Input Capture 2
1010
Timer Input Capture 3
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