參數(shù)資料
型號(hào)： MC68L11FC0PU3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： Technical Summary 8-Bit Microcontroller
中文描述： 8-BIT, MICROCONTROLLER, PQFP80
封裝： TQFP-80
文件頁(yè)數(shù)： 32/74頁(yè)
文件大?。?/td> 513K
代理商： MC68L11FC0PU3
MOTOROLA
MC68HC11F1/FC0
38
MC68HC11FTS/D
8 Chip-Selects
Chip selects eliminate the need for additional external components to interface with peripherals in ex-
panded non-multiplexed modes. Chip-select registers control polarity, address block size, base ad-
dress, and clock stretching.
8.1 Chip-Select Operation
There are four programmable chip selects on the MC68HC11F1 and MC68HC11FC0: two for external
I/O (CSIO1 and CSIO2), one for external program space (CSPROG), and one general-purpose chip se-
lect (CSGEN).
CSPROG is active low and becomes active at address valid time. CSPROG is enabled by the PCSEN
bit of the chip-select control register (CSCTL). Its address block size is selected by the PSIZA and
PSIZB bits of CSCTL.
Use the I/O chip selects (CSIO1 and CSIO2) for external I/O devices. These chip-select addresses are
found in the memory map block that contains the status and control registers. CSIO1 is mapped from
$x060 to $x7FF, and CSIO2 is mapped from $x800 to $xFFF, where x represents the REG[3:0] bits of
the INIT register on the MC68HC11F1 or the REG[1:0] bits of the INIT register on the MC68HC11FC0.
Polarity and enable-disable selections are controlled by CSCTL register bits IO1EN, IO1PL, IO2EN, and
IO2PL. The IO1AV and IO2AV bits of the CSGSIZ register determine whether the chip selects are valid
during address or E-clock valid times.
The general-purpose chip select is the most flexible of the four chip selects. Polarity, valid assertion
time, and block size are determined by the GNPOL, GAVLD, GSIZA, GSIZB, and GSIZC bits of the
CSGSIZ register. The starting address is selected with the CSGADR register.
Each of the four chip selects has two associated bits in the chip-select clock stretch register (CSSTRH).
These bits allow clock stretching from zero to three cycles (full E-clock periods) to accommodate slow
device interfaces. Any of the chip selects can be programmed to cause a clock stretch to occur only
during access to addresses that fall within that particular chip select’s address range.
During the stretch period, the E-clock is held high and the bus remains in the state that it is normally in
at the end of E high time. Internally, the clocks continue to run, which maintains the integrity of the timers
and baud-rate generators.
Priority levels are assigned to prevent the four chip selects from conflicting with each other or with in-
ternal memory and registers. There are two sets of priorities controlled by the value of the general-pur-
pose chip-select priority bit (GCSPR) of the CSCTL register. Refer to Table 17.
8.2 Chip-Select Registers
IO1SA, IOS1B — I/O Chip-Select 1 Clock Stretch
IO2SA, IO2SB — I/O Chip-Select 2 Clock Stretch
GSTHA, GSTHB — General-Purpose Chip-Select Clock Stretch
PSTHA, PSSTHB — Program Chip-Select Clock Stretch
Each pair of bits selects the number of clock cycles of stretch for the corresponding chip select.
CSSTRH — Clock Stretching
$x05C
Bit 7
6
5
4
3
2
1
Bit 0
IO1SA
IO1SB
IO2SA
IO2SB
GSTHA
GSTHB
PSTHA
PSTHB
RESET:
0
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