參數(shù)資料
型號: MC68L11F1CFNE3
廠商: Freescale Semiconductor
文件頁數(shù): 146/158頁
文件大小: 0K
描述: IC MCU 8BIT 3MHZ 68-PLCC
標準包裝: 18
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 3MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲器類型: ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
SERIAL COMMUNICATIONS INTERFACE
MC68HC11F1
7-2
TECHNICAL DATA
Figure 7-1 SCI Transmitter Block Diagram
7.3 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift register
receives data and transfers it to a parallel receive data register (SCDR) as a complete
word. This double buffered operation allows a character to be shifted in serially while
another character is already in the SCDR. An advanced data recovery scheme distin-
guishes valid data from noise in the serial data stream. The data input is selectively
sampled to detect receive data, and a majority voting circuit determines the value and
integrity of each bit.
FE
NF
OR
IDLE
RDRF
TC
TDRE
SCSR INTERRUPT STATUS
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
SCCR2 SCI CONTROL 2
TRANSMITTER
CONTROL LOGIC
TCIE
TC
TIE
TDRE
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
PIN BUFFER
AND CONTROL
H (8) 76543210
L
10 (11) - BIT Tx SHIFT REGISTER
PD1/
TxD
SCDR Tx BUFFER
TRANSFER
Tx
BUFFER
SHIFT
ENABLE
JAM
ENABLE
PREAMBLE—JAM
1's
BREAK—JAM
0's
(WRITE-ONLY)
FORCE PIN
DIRECTION (OUT)
SIZE
8/9
WAKE
M
T8
R8
SCCR1 SCI CONTROL 1
TRANSMITTER
BAUD RATE
CLOCK
DDD1
8
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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