參數(shù)資料
型號(hào)： MC68HLC705KJ1CDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 97/144頁
文件大?。?/td> 1377K
代理商： MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
56
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
4.7.3 Instruction Set Summary
Table 4-6. Instruction Set Summary (Sheet 1 of 6)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HIN Z C
ADC #opr
ADC opr
ADC opr,X
ADC ,X
Add with Carry
A
← (A) + (M) + (C)
—
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ADD #opr
ADD opr
ADD opr,X
ADD ,X
Add without Carry
A
← (A) + (M)
—
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
AND #opr
AND opr
AND opr,X
AND ,X
Logical AND
A
← (A) ∧ (M)
— — —
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Arithmetic Shift Left (Same as LSL)
— —
DIR
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
6
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
— —
DIR
INH
IX1
IX
37
47
57
67
77
dd
ff
5
3
6
5
BCC rel
Branch if Carry Bit Clear
PC
← (PC) + 2 + rel ? C = 0
—————
REL
24
rr
3
BCLR n opr
Clear Bit n
Mn
← 0
—————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
5
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC
← (PC) + 2 + rel ? C = 1
—————
REL
25
rr
3
BEQ rel
Branch if Equal
PC
← (PC) + 2 + rel ? Z = 1
—————
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC
← (PC) + 2 + rel ? H = 0
—————
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC
← (PC) + 2 + rel ? H = 1
—————
REL
29
rr
3
C
b0
b7
0
b0
b7
C
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