參數(shù)資料
型號: MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 131/144頁
文件大小: 1377K
代理商: MC68HLC705KJ1CDWR2
Parallel I/O Ports
Port B
MC68HC705KJ1 — Rev. 2.0
Technical Data
MOTOROLA
Parallel I/O Ports
87
7.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output.
DDRB[3:2] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[3:2], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-8 shows the I/O logic of port B.
Address:
$0005
Bit 7
654321
Bit 0
Read:
0
See Notes
DDRB3
DDRB2
See Note
Write:
Reset:
00000000
= Unimplemented
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These bits are
available for read/write but are not available externally. Configuring them as inputs will ensure that the
pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
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