
Operating Modes and On-Chip Memory
M68HC11E Family Data Sheet, Rev. 5.1
34
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$1000
Port A Data Register
(PORTA)
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
I
0
I
$1001
Reserved
R
$1002
Parallel I/O Control Register
(PIOC)
Read:
STAF
STAI
CWOM
HNDS
OIN
PLS
EGA
INVB
Write:
Reset:
0
U
1
$1003
Port C Data Register
(PORTC)
Read:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Write:
Reset:
Indeterminate after reset
$1004
Port B Data Register
(PORTB)
Read:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
0
$1005
Port C Latched Register
(PORTCL)
Read:
PCL7
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
Write:
Reset:
Indeterminate after reset
$1006
Reserved
R
$1007
Port C Data Direction Register
(DDRC)
Read:
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Write:
Reset:
0
$1008
Port D Data Register
(PORTD)
Read:
0
PD5
PD4
PD3
PD2
PD1
PD0
Write:
Reset:
U
I
$1009
Port D Data Direction Register
(DDRD)
Read:
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
Write:
Reset:
0
$100A
Port E Data Register
(PORTE)
Read:
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Write:
Reset:
Indeterminate after reset
$100B
Timer Compare Force Register
(CFORC)
Read:
FOC1
FOC2
FOC3
FOC4
FOC5
Write:
Reset:
0
$100C
Output Compare 1 Mask Register
(OC1M)
Read:
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
Write:
Reset:
0
= Unimplemented
R
= Reserved
U = Unaffected
I = Indeterminate after reset
Figure 2-7. Register and Control Bit Assignments (Sheet 1 of 6)