List of Figures
Technical Data
MC68HC912D60A — Rev 3.0
16
List of Figures
MOTOROLA
14-3
14-4
14-5
8-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . . .227
16-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . .228
Block Diagram for Port7 with Output compare /
Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .229
Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .264
Serial Communications Interface Block Diagram . . . . . . . . . .265
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .277
SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .278
SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .279
Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .280
MI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
Biphase coding and error detection . . . . . . . . . . . . . . . . . . . .292
MI BUS Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
A typical MI Bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . .295
The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
User Model for Message Buffer Organization. . . . . . . . . . . . .308
32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .312
16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .312
8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .313
SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .319
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Segments within the Bit Time. . . . . . . . . . . . . . . . . . . . . . . . .323
msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
17-10 Message Buffer Organization. . . . . . . . . . . . . . . . . . . . . . . . .325
17-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
17-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
18-1
Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .350
19-1
BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .381
19-2
BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .381
19-3
BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .382
20-1
Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
20-2
POR and External Reset Timing Diagram . . . . . . . . . . . . . . .415
20-3
STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .416
20-4
WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .417
20-5
Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
20-6
Port Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .419
20-7
Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419
14-6
15-1
15-2
15-3
15-4
15-5
15-6
16-1
16-2
16-3
16-4
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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