參數(shù)資料
型號： MC68HC705SR3PE
廠商： Freescale Semiconductor
文件頁數(shù)： 87/96頁
文件大?。?/td> 0K
描述： IC MCU 3.75K 2.1MHZ OTP 40-DIP
標(biāo)準(zhǔn)包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： LED，POR
輸入/輸出數(shù)： 32
程序存儲器容量： 3.75KB（3.75K x 8）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
Freescale
A-2
MC68HC05SR3
MC68HC705SR3
A
A.2
Modes of Operation
The MC68HC705SR3 has two modes of operation – user mode and EPROM bootstrap mode.
Table A-1 shows the conditions required to enter each mode on the rising edge of RESET.
A.3
User Mode
The normal operating mode of the MC68HC705SR3 is the user mode. User mode will be entered
on the rising edge of RESET when the VPP and PB1 pins are between VSS and VDD.
Warning: In the MC68HC705SR3, all vectors are fetched from EPROM in user mode; therefore,
the EPROM must be programmed (via the bootstrap mode) before the device is
powered up in user mode.
A.4
Bootstrap Mode
The bootstrap mode is provided as a mean of self-programming MC68HC705SR3 EPROM with
minimal circuitry, and can only run in the crystal oscillator mode. Bootstrap mode will be entered
on the rising edge of RESET when the VPP pin is at VTST (2×VDD) and PB1 pin is at VDD. Once
in the bootstrap mode, PB1 can then be used for other purposes. After entering the bootstrap
mode, CPU branches to the bootstrap program and carries out the EPROM programming routine.
The user EPROM consists of 3840 bytes, from location $1000 to $1EFF.
This program handles copying of user code from an external EPROM into the on-chip EPROM.
The bootstrap function does not have to be done from an external EPROM, but it may be done
from a host.
The user code must be a one-to-one correspondence with the internal EPROM addresses.
Table A-1 MC68HC705SR3 Operating Mode Entry Conditions
RESET
VPP
PB1
MODE
VSS to VDD
USER
VTST
VDD
BOOTSTRAP
VTST=2×VDD
5V
TPG
86
05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM
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