參數(shù)資料
型號(hào): MC68HC705SR3PE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 37/96頁(yè)
文件大小: 0K
描述: IC MCU 3.75K 2.1MHZ OTP 40-DIP
標(biāo)準(zhǔn)包裝: 9
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: LED,POR
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 3.75KB(3.75K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
Freescale
5-6
MC68HC05SR3
RESETS AND INTERRUPTS
5
Figure 5-3 External Interrupt
+
&
EXTERNAL
REQUEST
INTERRUPT
POWER-ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED (IRQ ONLY)
D
C
R
Q
VDD
INTO BIT
I-BIT (CCR)
IRQ
tILIH
tILIL
EDGE SENSITIVE TRIGGER
CONDITION
The minimum pulse width tILIH is either
125ns (VDD=5V) or 250ns (VDD=3V).
The period tILIL should not be less than
the number of tcyc cycles it takes to ex-
ecute the interrupt service routine plus
21 tCYC cycles.
tILIH
Wired ORed
Interrupt signals
IRQ
if after servicing an interrupt the
external interrupt pin (IRQ) remains
low, then the next interrupt is
recognized. Normally used with pull-up
resistors for wired-OR connection.
(b) Interrupt Mode Diagram
(a) Interrupt Function Diagram
LEVEL SENSITIVE TRIGGER
CONDITION
+
&
IRQ
100K
VDD
TPG
40
05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM
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