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| 型號(hào)： | MC68HC705SR3PE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 63/96頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 3.75K 2.1MHZ OTP 40-DIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | LED，POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 3.75KB（3.75K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | OTP |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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Freescale
8-12
MC68HC05SR3
CPU CORE AND INSTRUCTION SET
8
8.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Freescale assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
EA = (PC+1):(PC+2); PC
← PC+3
Address bus high
← (PC+1); Address bus low ← (PC+2)
8.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC
← PC+1
Address bus high
← 0; Address bus low ← X
8.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC
← PC+2
Address bus high
← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
8.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Freescale
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC
← PC+3
Address bus high
← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
TPG
64
05SR3.Book Page 12 Thursday, August 4, 2005 1:08 PM
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