參數(shù)資料
型號(hào): MC68HC705P6AMDW
廠商: Freescale Semiconductor
文件頁數(shù): 91/98頁
文件大小: 0K
描述: IC MCU 4.6K OTP 2.1MHZ 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 4.5KB(4.5K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
MC6
8
HC70
5
P6A
Ad
v
a
nce
Inf
o
rm
ation
Da
ta
Shee
t,
Re
v
.
2
.1
Fre
e
scale
Semico
nductor
91
Control
Timing
Figure 14-2. Power-On Reset and External Reset Timing Diagram
PCH
PCL
OSC1
(2)
RESET
INTERNAL
PROCESSOR
INTERNAL
ADDRESS
BUS
(1)
1FFE
1FFF
V
DD
V
DD
THRESHOLD (1-2 V TYPICAL)
t
VDDR
4064 t
cyc
t
cyc
tRL
INTERNAL
DATA
BUS
(1)
1FFE
NEW PC
1FFF
Notes:
1.
Internal timing signal and bus information are not available externally.
2.
OSC1 line is not meant to represent frequency. It is only used to represent time.
3.
The next rising edge of the internal clock following the rising edge of RESET initiates the reset sequence.
NOTE 3
NEW
OP
CODE
PCL
PCH
NEW PC
OP
CODE
NEW PC
CLOCK
(1)
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