參數(shù)資料
型號(hào)： MC68HC705P6AMDW
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 26/98頁(yè)
文件大小： 0K
描述： IC MCU 4.6K OTP 2.1MHZ 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 21
程序存儲(chǔ)器容量： 4.5KB（4.5K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 176 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Resets
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
32
Freescale Semiconductor
The POR will generate the RST signal and reset the MCU. If any other reset function is active at the end
of this 4064 internal clock cycle delay, the RST signal will remain active until the other reset condition(s)
end.
4.3.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (COP bit in the MOR is set), the internal COP reset is
generated automatically by a timeout of the COP watchdog timer. This timer is implemented with an
18-stage ripple counter that provides a timeout period of 65.5 ms when a 4-MHz oscillator is used. The
COP watchdog counter is cleared by writing a logical 0 to bit zero at location $1FF0.
The COP watchdog timer can be disabled by clearing the COP bit in the MOR or by applying 2 x VDD to
the IRQ/VPP pin (for example, during bootloader). When the IRQ/VPP pin is returned to its normal
operating voltage range (between VSS–VDD), the COP watchdog timer’s output will be restored if the COP
bit in the mask option register (MOR) is set.
The COP register is shared with the least significant byte (LSB) of an unused vector address as shown
in Figure 4-2. Reading this location will return the programmed value of the unused user interrupt vector,
usually 0. Writing to this location will clear the COP watchdog timer.
When the COP watchdog timer expires, it will generate the RST signal and reset the MCU. If any other
reset function is active at the end of the COP reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end. When the reset condition ends, the MCU’s operating mode will be
Address:
$1FF0
Bit 7
654321
Bit 0
Read:
00000000
Write:
COPR
= Unimplemented
Figure 4-2. Unused Vector and COP Watchdog Timer
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