參數(shù)資料
型號: MC68HC705P6ACSD
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù): 80/130頁
文件大小: 1541K
代理商: MC68HC705P6ACSD
Input/Output Ports
Port B
MC68HC705P6A — Rev. 2.0
Advance Information
MOTOROLA
Input/Output Ports
53
6.4 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with
the SIOP communications subsystem. The port B data register is located
at address $0001 and its data direction register (DDR) is located at
address $0005. The contents of the port B data register are
indeterminate at initial powerup and must be initialized by user software.
Reset does not affect the data registers, but clears the DDRs, thereby
setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode (see Figure 6-2).
Port B may be used for general I/O applications when the SIOP
subsystem is disabled. The SPE bit in register SPCR is used to
enable/disable the SIOP subsystem. When the SIOP subsystem is
enabled, port B registers are still accessible to software. Writing to either
of the port B registers while a data transfer is under way could corrupt
the data. See Section 7. Serial Input/Output Port (SIOP) for a
discussion of the SIOP subsystem.
Figure 6-2. Port B I/O Circuitry
READ $0001
WRITE $0001
READ $0005
DATA
REGISTER BIT
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0005
DATA DIRECTION
REGISTER BIT
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PDF描述
MCHC705P6ACSDR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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