參數(shù)資料
型號(hào): MC68HC705P6ACSD
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù): 103/130頁
文件大?。?/td> 1541K
代理商: MC68HC705P6ACSD
Capture/Compare Timer
Advance Information
MC68HC705P6A — Rev. 2.0
74
Capture/Compare Timer
MOTOROLA
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
Address:
OCRH — $0016
Bit 7
6
54
32
1
Bit 0
Write:
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Read:
Unaffected by reset
Address:
OCRL — $0017
Bit 7
6
54
32
1
Bit 0
Read:
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
相關(guān)PDF資料
PDF描述
MCHC705P6ACSDR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
MC68HC705P6AMP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
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