參數(shù)資料
型號： MC68HC705P6A
廠商： Motorola, Inc.
英文描述： HCMOS Microcontroller Unit
中文描述： HCMOS微控制器
文件頁數(shù)： 92/130頁
文件大?。?/td> 1541K
代理商： MC68HC705P6A
Mask Option Register (MOR)
Advance Information
MC68HC705P6A
—
Rev. 2.0
92
Mask Option Register (MOR)
MOTOROLA
COP
—
COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will
reset the MCU if the timeout period is reached before the COP
watchdog timer is cleared by the application software
and
the voltage
applied to the IRQ/V
PP
pin is between V
SS
and V
DD
. Clearing the
COP bit will disable the COP watchdog timer regardless of the voltage
applied to the IRQ/V
PP
pin.
LEVEL
—
IRQ Edge Sensitivity
If the LEVEL bit is clear, the IRQ/V
PP
pin will only be sensitive to the
falling edge of the signal applied to the IRQ/V
PP
pin. If the LEVEL bit
is set, the IRQ/V
PP
pin will be sensitive to both the falling edge of the
input signal and the logic low level of the input signal on the IRQ/V
PP
pin.
LSBF
—
SIOP Least Significant Bit First
If the LSBF bit is set, the serial data to and from the SIOP will be
transferred least significant bit first. If the LSBF bit is clear, the serial
data to and from the SIOP will be transferred most significant bit first.
Address: $1EFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Erased State:
0
0
0
0
0
0
0
0
Address: $1F00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SECURE
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
Write:
Erased State:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-1. Mask Option Register (MOR)
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