參數(shù)資料
型號(hào)： MC68HC705P6A
廠商： Motorola, Inc.
英文描述： HCMOS Microcontroller Unit
中文描述： HCMOS微控制器
文件頁數(shù)： 39/130頁
文件大小： 1541K
代理商： MC68HC705P6A
Operating Modes
Low-Power Modes
MC68HC705P6A
—
Rev. 2.0
Advance Information
MOTOROLA
Operating Modes
39
The MCU can be brought out of stop mode only by an IRQ external
interrupt or an externally generated RESET. When exiting stop mode,
the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.
NOTE:
Execution of the STOP instruction when the SWAIT bit in the MOR is
clear will cause the oscillator to stop, and, therefore, disable the COP
watchdog timer. To avoid turning off the COP watchdog timer, stop
mode should be changed to halt mode by setting the SWAIT bit in the
MOR. See
3.6 COP Watchdog Timer Considerations
for additional
information.
3.5.1.2 Halt Mode
NOTE:
Halt mode is
NOT
designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. This mode of operation is usually
achieved by invoking wait mode.
Execution of the STOP instruction when the SWAIT bit in the MOR is set
places the MCU in this low-power mode. Halt mode consumes the same
amount of power as wait mode (both halt and wait modes consume more
power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
the halt mode and resume normal operation. The halt mode also can be
exited when an IRQ external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay
of one to 4064 internal clock cycles. This varied delay time is the result
of the halt mode exit circuitry testing the oscillator stabilization delay
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