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參數(shù)資料
| 型號： | MC68HC11KA4TS |
| 廠商： | Motorola, Inc. |
| 英文描述： | KPT 3C 3#16 PIN PLUG |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 36/68頁 |
| 文件大小： | 365K |
| 代理商： | MC68HC11KA4TS |
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MOTOROLA
36
MC68HC11KA4
MC68HC11KA4TS/D
Port H pins reset to high-impedance inputs with selectable internal pull-up resistors.
Bits [7:4] — Not implemented
Always read zero
DDH[3:0] — Data Direction for Port H
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
NOTE
In any mode, PWM circuitry forces the I/O state to be an output for each port H line
associated with an enabled pulse-width modulator channel. In these cases, data
direction bits are not changed and have no effect on these lines. DDRH reverts to
controlling the I/O state of a pin when the associated function is disabled. Refer to
12 Pulse-Width Modulation Timer
for further information.
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W.
DDG7 — Data Direction for Port G
0 = Bit set to zero to configure corresponding I/O pin for input only
1 = Bit set to one to configure corresponding I/O pin for output
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero.
Bits [6:0] — Not implemented
Always read zero
PORTH
— Port H Data
$007C
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
PH3
PH2
PH1
PH0
RESET:
0
0
0
0
U
U
U
U
Alt. Pin
Func.:
—
—
—
—
PW4
PW3
PW2
PW1
DDRH
— Data Direction Register for Port H
$007D
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
DDH3
DDH2
DDH1
DDH0
RESET:
0
0
0
0
1
1
1
1
PORTG
— Port G Data
$007E
Bit 7
6
5
4
3
2
1
Bit 0
PG7
—
—
—
—
—
—
—
RESET:
U
0
0
0
0
0
0
0
Alt. Pin
Func.:
R/W
—
—
—
—
—
—
—
DDRG
— Data Direction Register for Port G
$007F
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
—
—
—
—
—
—
—
RESET:
0
0
0
0
0
0
0
0
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