參數(shù)資料
型號(hào)： MC68HC11KA4TS
廠商： Motorola, Inc.
英文描述： KPT 3C 3#16 PIN PLUG
中文描述： 8位微控制器
文件頁(yè)數(shù)： 32/68頁(yè)
文件大?。?/td> 365K
代理商： MC68HC11KA4TS
MOTOROLA
32
MC68HC11KA4
MC68HC11KA4TS/D
LIRDV — LIR Driven
Refer to
2 Operating Modes and On-Chip Memory
.
CWOM — Port C Wired-OR Mode
0 = Port C operates normally.
1 = Port C outputs are open-drain.
Bit 5 — Not implemented
Always reads zero
IRVNE — Internal Read Visibility/Not E
Refer to
2 Operating Modes and On-Chip Memory
.
LSBF — SPI LSB First Enable
Refer to
8 Serial Peripheral Interface
.
SPR2 — SPI Clock (SCK) Rate Select
Refer to
8 Serial Peripheral Interface
.
XDV1, XDV0 — XOUT Clock Divide Select
Refer to
2 Operating Modes and On-Chip Memory
.
NOTE
Do not confuse pin function with the electrical state of the pin at reset. All general-
purpose I/O pins configured as inputs at reset are in a high-impedance state and
the contents of port data registers is undefined. In port descriptions, a “U” indicates
this condition. The pin function is mode dependent.
NOTE
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Oth-
erwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being
cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled,
writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5
has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse ac-
cumulator input but also can be configured for general-purpose I/O, or output com-
pare. Note that even when PA7 is configured as an output, the pin still drives the
pulse accumulator input.
OPT2
—System Configuration Options 2
$0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
—
IRVNE
LSBF
SPR2
XDV1
XDV0
RESET:
0
0
0
—
0
0
0
0
PORTA
—Port A Data
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
U
U
U
U
U
U
U
U
Alt. Pin
Func.:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
—
—
—
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