參數(shù)資料
型號(hào)： MC68HC11KA4TS
廠商： Motorola, Inc.
英文描述： KPT 3C 3#16 PIN PLUG
中文描述： 8位微控制器
文件頁(yè)數(shù)： 28/68頁(yè)
文件大小： 365K
代理商： MC68HC11KA4TS
MOTOROLA
28
MC68HC11KA4
MC68HC11KA4TS/D
DLY —Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
CME — Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME — Force Clock Monitor Enable
0 = Clock monitor follows the state of the CME bit
1 = Clock monitor circuit is enabled until next reset
CR[1:0] — COP Timer Rate Select
Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP
watchdog.
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
RBOOT — Read Bootstrap ROM
Refer to
2 Operating Modes and On-Chip Memory
.
SMOD — Special Mode Select
Refer to
2 Operating Modes and On-Chip Memory
.
MDA — Mode Select A
Refer to
2 Operating Modes and On-Chip Memory
.
Table 6 COP Timer Rate Select
CR[1:0]
Divide
E/2
15
By
XTAL = 8.0 MHz
Time-out
–0/+16.4 ms
16.384 ms
65.536 ms
262.14 ms
1.049 s
2.0 MHz
XTAL = 12.0 MHz
Time-out
–0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
XTAL = 16.0 MHz
Time-out
–0/+8.2 ms
8.192 ms
32.768 ms
131.07 ms
524.29 ms
4.0 MHz
0 0 0
0 0 1
0 1 0
0 1 1
1
4
16
64
E =
COPRST
— Arm/Reset COP Timer Circuitry
$003A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
HPRIO
— Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT*
SMOD*
MDA*
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
—
—
—
0
0
1
1
0
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